The present disclosure relates to techniques for extracting interconnect impedance properties, such as inductance, of an integrated circuit.
Metal interconnects are an important part of integrated circuits. Partly because on-chip metal interconnects tend to be denser, faster, and more reliable than off-chip connections, there is a continuing drive toward higher levels of chip integrations. This continuing drive in turn places more and more stringent requirements on the properties of on-chip metal interconnects.
Metal interconnects play several crucial roles including forming signal lines and providing networks for power distribution and ground distribution. An ideal metal interconnect should play no active role in the integrated circuit other than conducting electrons, but actual metal interconnects are not ideal. Real metal interconnects are characterized by matrices of resistance (R), inductance (L), capacitance (C), and conductance (G). Each of these fundamental impedance properties could be a factor that must be taken into account in the design of the integrated circuit. This requires that the designers of the integrated circuit have knowledge of these impedance properties with respect to a certain design layout of the integrated circuit. Specific knowledge of these impedance properties is required to check, commonly using a computational simulation and modeling method, whether a particular design meets the design objective. If it does, the design is accepted. If it does not, changes are made in the design, interconnect impedance properties of the new design are obtained if necessary, and additional simulation is performed. The process is repeated until a satisfactory design is achieved.
One of the impedance (R, L, C and G) related effects of metal interconnects is signal delay. As the signal switching speeds exceed 1 GHz and chip densities exceed tens of millions of transistors, signal delay caused by the on-chip metal interconnects becomes significant. Interconnect signal delay may be contributed by any impedance properties. RC delay (delay caused by resistance and capacitance), for example, has prompted an industry-wide shift from aluminum to copper interconnects to reduce the resistance, and a search for a dielectric material with low-permittivity to reduce the capacitance. However, although use of better materials may reduce the RC delay, it does not eliminate them. In addition, these measures are less effective in reducing the delays dominated by inductance.
In particular, as operating frequencies of integrated circuits continue to rise, the effect of inductance on circuit performance is becoming increasingly important, requiring a more complete RLC model for simulation. For example, high-speed VLSI exhibits subnanosecond switching and requires clock signal propagation bandwidth above 1 GHz in order to maintain rise times. Under such frequency ranges, the self inductance of a signal wire can create a signal-delay problem.
In addition to causing signal delay, inductance also contributes signal noise in an integrated circuit. Signal noise and cross-talk largely relate to the mutual inductance among neighboring signal wires and may create signal-integrity problems. As has been observed in early high-speed microprocessors (P. J. Restle et al., “Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor,” IEEE Journal of solid-state circuits, vol. 33, no. 4, April 1998, pp. 662-665), inductance is believed to be a main contributor to Simultaneous Switching Noise (SSN) in high-speed VLSI designs.
Correspondingly, the effective modeling and analysis of impedance, particularly that of inductance, has become an issue of great interest for high-speed circuit designing over the years to suit the ever-higher operation frequency. This has created a growing need for extracting interconnect impedance properties (R, L, C and G) to be used with development tools such as electronic design automation (EDA) software for creating, simulating, and verifying designs.